init:
	addi r30, r0, 1
	addi r29, r0, 6		; this is because logic is lazy =)
	addi r28, r0, 1		; this too

main:

	addi r12, r0, 0

main4:
	lessthan r15, r29, r12
	pred r15, r30
	branchi r0, main2

	addi r13, r0, 0

main3:
	lessthan r15, r12, r13
	pred r15, r30
	branchi r0, main1

	add r1, r0, r12
	add r2, r0, r13

	branchi r0, comb

	systemi 2

	addi r13, r13, 1
	branchi r0, main3

main1:
	systemi 5

	addi r12, r12, 1
	branchi r0, main4

main2:
	systemi 1

fact:
	add r26, r0, r31 ; save return address (logic)
	lessthani r15, r1, 2
	pred r15, r30
	addi r1, r0, 1

	pred r15, r30
	branch r0, r31

	add r11, r0, r2
	add r2, r0, r1

fact1:
	subi r1, r1, 1
	mul r2, r2, r1

	lessthan r15, r28, r1
	pred r15, r30
	branchi r0, fact1

	add r1, r0, r2
	add r2, r0, r11
	
	branch r0, r26

comb:
        add r27, r0, r31 ; save return address (logic)
	add r3, r0, r1
	add r4, r0, r2

	branchi r0, fact

	add r5, r0, r1

	add r1, r0, r2
	branchi r0, fact
	add r6, r0, r1

	sub r1, r3, r4
	branchi r0, fact

	mul r1, r6, r1
	div r1, r5, r1
	
	branch r0, r27 ; return to caller (logic)